1. Field of the Invention
The invention relates to a circuit for confirming a connection route of ACM (Address Control Memory). More particularly, it relates to a circuit for confirming a connection route of ACM used for a time switch which voluntarily changes in a time slot position of time-division multiplexed data.
2. Description of the Related Art
FIG. 6 is a block diagram showing an example of a conventional digital telephone circuit. As shown in this figure, conventional digital telephone circuits encode a voice signal transmitted from a plurality of mouthpiece 61a, in a coding unit 62 into a digitalized and compressed form followed by converting the encoded signal from parallel to serial into a multiplexed form in a multiplexing unit 63 so that such signal is concentrated and exchanged at a relay transmitting unit 64 which includes a concentrating and switching unit 64a which includes concentrating and switching unit 64a.
The exchanged voice signal is converted from serial to parallel at a demultiplexing circuit or unit 65 into a demultiplexed form. Then, the voice signal is decoded into an analog form in a decoding circuit or unit 66. The analog voice signal is transmitted to each telephone receiver 61b.
FIG. 7 is a block diagram showing an arrangement of a position of the time switch provided in the relay transiting unit 64. As this figure shows, the voice signal sent from each telephone 61 passes through the respective coding unit 62 and is converted from parallel to serial at the multiplexing unit 63. Then, the voice signal is concentrated and exchanged at the relay transmitting unit 64 (shown in FIG. 6). When the relay transmitting unit 64 exchanges the voice signal, the position of the data or signal in a time slot is changed by a time switch 68.
The signal having thus changed its position in a time slot is converted from serial to parallel at the demultiplexing unit 65, and is transmitted to each telephone 61 through the respective decoding unit 66.
FIG. 8 is a block diagram showing a structure of the conventional time switch 68. As shown in this figure, the time switch 68 which voluntarily changes the position of the time-division multiplexed data with the passage of time comprises a data memory 81 for storing data entered in each position in a time slot, an address counter 82 for counting a clock signal cyclically and an address control memory 83 for memorizing the position of the data in a time slot to be changed with respect to the entered data.
The time switch 68 is available in two types. One has a structure of sequential write/random read shown in FIG. 8 in which the address control memory 83 is arranged on the side of the data memory 81 at which the reading address is designated, and the other has an opposite structure of random write/sequential read shown in FIG. 9 in which the address control memory 83 is arranged on the side of the data memory 81 at which the writing address is designated.
The time switch 68 having sequential write/random read structure as shown in FIG. 8 performs the following processing when data is entered in which one-cycle time slot positions are set in the order of A, B and C, and a sequence of data thus entered is output with the time slot position thereof being converted into the order of C, A and B.
At the time of data writing to the data memory 81, the addresses are designated sequentially based on the address values counted by the address counter 82, and the entered serial data are written into the data memory 81 in the order of A, B and C (sequential write).
At the time of data reading, the address values counted by the address counter 82 are changed by the address control memory 83 and the data are read from the data memory 81 in the order of C, A and B in accordance with the changed address values (random read).
Namely, according to the time switch 68 having the sequential write/random read structure shown in FIG. 8, the address values 1, 2 and 3 counted by the address counter 82 are changed to the values of 3, 1 and 2 by the address control memory 83.
On the other hand, the time switch 68 having random write/sequential read structure performs the following processing to do the same work as mentioned above.
As shown in FIG. 9, at the time of data writing to the data memory 81, the address values counted by the address counter 82 are changed by the address control memory 83, and the entered serial data are written to the data memory 81 in the order of C, A and B in accordance with the changed addresses (random write).
At the time of data reading, the addresses are designated sequentially based on the address values counted by the address counter 82, and the data are read from the data memory 81 in the order of C, A and B (sequential read).
Namely, according to the time switch 68 having the random write/sequential read structure shown in FIG. 9, the address values 1, 2 and 3 counted by the address counter 82 are changed to the values of 2, 3 and 1 by the address control memory 83.
However, in case of circuit failures conventional time switches 68 require the confirmation of a position of data in the time slot at the time of data writing from the position of data in the time slot at the time of data reading or a position of data in a time slot at the time of data reading from the position in the time slot at the time of data writing, such time switches have a disadvantage that all the data stored in the address control memory 83 have to be read at maximum for the confirmation of changed data of the data position in the time slot written into the address control memory 83 (where the data entered in a certain position at the time of writing is output from that at the time of reading) in bits.
For example, according to the time switch 68 having the sequential write/random read structure shown in FIG. 8, the data in the second position of the time slot in the address control memory 83 is read in order to confirm where the position of the data in the second position of the time slot on the output side is located on the input side. It is instantly found that the data in the second position of the time slot on the input side is the data in the first position of the time slot on the output side.
However, in order to confirm where the position of the data in the second position of the time slot on the input side is located on the output side, it is necessary to sequentially read all the data in the address control memory 83. Accordingly, it is impossible to judge that the data in the second position of the time slot on the input side is located in the third position of the time slot on the output side, until confirming that the data having the value of "2" corresponds to the address of "3" in the address control memory 83.
As the result, in the time switch 68 having the sequential write/random read structure, the position of the time slot on the input side can be instantly examined from the output side, but it requires a long time to examine the position of the time slot on the output side from the position of the time slot on the input side.
On the other hand, in the time switch 68 having the random write/sequential read structure, the position in the time slot on the output side can be instantly examined from the input side, but it requires a long time to examine the data position in the time slot on the input side from the data position in the time slot on the output side.
As the conventional time switches are known a time switch for a time-division exchange disclosed in Japanese Unexamined Patent Publication 62(1987)-264798 and a time-division space switch disclosed in Japanese Unexamined Patent Publication 62(1987)-265888.
Further, as an address control is known a scanning method disclosed in Japanese Unexamined Patent Publication 53(1978)-47706, and an address designating device is disclosed in Japanese Unexamined Patent Publication 4(1992)-60563, and a device having a circuit for maintaining an address control memory is disclosed in Japanese Unexamined Patent Publication 4(1992)-321151.